1. Field of the Invention
Generally, the subject matter disclosed herein relates to the field of manufacturing integrated circuits, and, more particularly, to chemical mechanical polishing (CMP) process techniques used for the formation of metallization structures of semiconductor devices.
2. Description of the Related Art
Typically, the fabrication of modern integrated circuits requires a large number of individual process steps, wherein a typical process sequence involves the deposition of conductive, semiconductive or insulating layers on an appropriate substrate. After deposition of the corresponding layer, device features are produced by patterning the corresponding layer with well-known means, such as photolithography and etching. As a consequence, by patterning a deposited layer, a certain topography will be created that also affects deposition and patterning of subsequent layers. Since sophisticated integrated circuits require the formation of a plurality of subsequent levels, it has become standard practice to periodically planarize the surface of the substrate to provide well-defined conditions for deposition and patterning of subsequent material layers. This holds especially true for so-called metallization layers in which metal interconnects are formed to electrically connect the individual device features, such as transistors, capacitors, resistors and the like, to establish the functionality required by the circuit design.
In this respect, CMP has become a widely used process technique for reducing “imperfections” in the substrate topography caused by preceding processes in order to establish enhanced conditions for a subsequent process, such as photolithography and the like. Although the polishing process itself causes mechanical damage to the polished surface, however, in an extremely low range, i.e., at an atomic level, depending on the process conditions, unwanted material may be removed at moderately high rates and with a relatively high degree of uniformity. However, CMP processes also have a plurality of side effects that have to be addressed so as to be applicable to processes required for forming sophisticated semiconductor devices.
For example, the so-called damascene or inlaid technique has become a preferred method in forming metallization layers, wherein a dielectric layer is deposited and patterned to receive trenches and vias that are subsequently filled with an appropriate metal, such as aluminum, copper, copper alloys, silver, tungsten and the like. Since the process of providing the metal may be performed as a “blanket” deposition process based on, for instance, electrochemical deposition techniques, the respective pattern of the dielectric material may require a significant over-deposition in order to reliably fill narrow openings and wide regions or trenches in a common process. The excess metal is then removed and the resulting surface is planarized by performing a process sequence comprising one or more mechanical polishing processes, which also include a chemical component. Chemical mechanical polishing (CMP) has proven to be a reliable technique to remove the excess metal and planarize the resulting surface so as to leave behind metal trenches and vias that are electrically insulated from each other as required by the corresponding circuit layout. Chemical mechanical polishing typically requires the substrate to be attached to a carrier, a so-called polishing head, such that the substrate surface to be planarized is exposed and may be placed against a polishing pad. The polishing head and polishing pad are moved relative to each other usually by individually moving the polishing head and the polishing pad. Typically, the head and pad are rotated against each other while the relative motion is controlled to locally achieve a target material removal rate. During the polishing operation, typically a slurry that may include a chemically reactive agent and possibly abrasive particles is supplied to the surface of the polishing pad.
One problem involved in the chemical mechanical polishing of substrates is the very different removal rates of differing materials, such as of a metal and a dielectric material from which the excess metal has to be removed. For instance, at a polishing state where the dielectric material and the metal are simultaneously treated, i.e., after the major portion of the metal has already been removed, the removal rate for the metal typically exceeds the removal rate for the dielectric material. This may be desirable to a certain degree because all metal is to be reliably ablated from all insulating surfaces, thereby insuring the required electrical insulation. On the other hand, significant metal removal from trenches and vias may result in a trench or via that exhibits an increased electrical resistance due to the reduced cross-sectional area. Moreover, the local removal rate may significantly depend on the local structure, i.e., on the local pattern density, which may result in a locally varying degree of erosion of the dielectric material in a final state of the polishing process. In order to more clearly demonstrate a typical damascene process, reference is made to FIGS. 1a-1c. 
FIGS. 1a-1c schematically show cross-sectional views of a semiconductor structure 100 at various stages in fabricating a metallization layer according to a typical damascene process sequence.
In FIG. 1a, the semiconductor structure 100 comprises a substrate 101 bearing circuit features (not shown) and an insulating cap layer on which metal lines are to be formed. A patterned dielectric layer 102 is formed over the substrate 101 and includes openings, for example, in the form of narrow trenches 103 and wide trenches 104. The openings for trenches 103 and 104 are patterned in conformity with design rules of the metallization level under consideration to establish metal lines exhibiting the required electrical characteristics in terms of functionality and conductivity. For instance, the trench 104 is designed as a so-called wide line to provide low electrical resistance. The deposition of the dielectric material 102, as well as the patterning of the trenches 103 and 104, is carried out by well-known deposition, etching and photolithography techniques.
FIG. 1b schematically depicts the semiconductor structure 100 after deposition of a metal layer 105, for example, a copper layer when sophisticated integrated circuits are considered. As is evident from FIG. 1b, the topography of the metal layer 105 will be affected by the underlying pattern of the dielectric layer 102. The metal layer 105 may be deposited by chemical vapor deposition, sputter deposition or, as usually preferred with copper, by electroplating with a preceding sputter deposition of a corresponding copper seed layer. Although the precise shape of the surface profile of the metal layer 105 may depend on the deposition technique used, in principle, a surface topography will be obtained as shown in FIG. 1b. 
Subsequently, the semiconductor structure 100 will be subjected to the chemical mechanical polishing in which, as previously mentioned, the slurry and polishing pad are selected to optimally remove the excess metal in the metal layer 105. During the chemical mechanical polishing, the excess metal is removed and finally surface portions 108 (FIG. 1c) of the dielectric material 102 will be exposed, wherein it is necessary to continue the polishing operation for a certain overpolish time to ensure clearance of the metal from all insulating surfaces in order to avoid any electrical short between adjacent metal lines. As previously mentioned, the removal rate of the dielectric material and the metal may significantly differ from each other so that upon overpolishing of the semiconductor structure 100, the copper in the trenches 103 and 104 will be recessed.
FIG. 1c schematically shows a typical result of chemical mechanical polishing the structure shown in FIG. 1b. As is evident from FIG. 1c, during overpolishing of the semiconductor structure 100, different materials are simultaneously polished with different removal rates. The removal rate is also dependent to some degree on the underlying pattern. For instance, the recessing of the metals during the overpolish time, which is also referred to as dishing, as well as the removal of the dielectric material, also referred to as erosion, is significantly affected by the type of pattern to be polished. In FIG. 1c, dishing and erosion at the wide trenches 104, as indicated by 107 and 106, respectively, are relatively moderate, whereas at the narrow lines 103, dishing 107 and erosion 106 may be significantly increased. For obtaining a required electrical conductivity, circuit designers have to take into consideration a certain degree of dishing and erosion, which may not be compatible with design requirements of sophisticated semiconductor devices.
Consequently, the CMP process used for removing excess material and planarizing the resulting surface topography of metallization layers has to be performed on the basis of tightly set parameter ranges, in particular when highly scaled semiconductor devices are considered. Therefore, in addition to complex control strategies used for advanced CMP processes, appropriate measurement data are usually generated on the basis of respective test structures, as will be described in more detail with reference to FIG. 1d. 
FIG. 1d schematically illustrates a cross-sectional view of the semiconductor device 100, which now comprises a test area 150 for evaluating the CMP process used for removing excess material during the formation of the metal regions 104, 105 in a device area, as previously described with reference to FIGS. 1a-1c. For this purpose, the metallization level under consideration, indicated as metallization layer 110, comprises a pair of metal regions 151, i.e., respective metal lines 151A, 151B, which may be formed on the basis of the respective design rules of the metallization layer 110 and of respective design rules of a metallization layer located below the layer 110. Thus, the metal lines 151A, 151B may be formed on the basis of the same process sequence as previously described, wherein, during the removal of the excess material, depending on the quality of the respective CMP process, metal residues may still be present between the metal lines 151A, 151B. For instance, it may be assumed that the CMP process may result in the creation of metal residues, for instance, due to a variation of one or more process parameters, thereby resulting in a leakage path 153, which may be comprised of a barrier material 111, which is typically used in combination with copper-based metallization layers, and a respective copper material. Thus, after the deposition of the insulating cap layer 109, which may be comprised of silicon nitride, nitrogen-enriched silicon carbide and the like, a conductive path may be established between the metal lines 151A, 151B, which may be electrically detected by connecting the lines 151A, 151B to an external electrical test device. For this purpose, an appropriate interconnect structure may be provided in the test area 150 to enable access to the metal lines 151A, 151B at any appropriate manufacturing stage. For example, the metal lines 151A, 151B may be accessed after forming the metallization layer 110, thereby providing feedback measurement data for controlling the CMP process for subsequent semiconductor devices. Although a certain degree of evaluation of the CMP process may be accomplished on the basis of the test area 150, the determination of the current performance of the CMP process in a more quantitative manner is very difficult, since the test structure defining the metal lines 151A, 151B may allow a respective quantitative assessment when the leakage path 153 is actually created during the CMP process. Thus, with respect to identifying the “position” of the currently used set of parameters within the tightly set “process window” of the CMP process, the amount of information obtained from the test structure 150 may not be sufficient.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.